In general, a dynamic random access memory (DRAM) interrupts a power voltage supplied to an internal circuit to reduce unnecessary current consumption when it enters into a deep power down mode or a power down mode.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, a semiconductor memory device comprises a control signal generating unit 1 and a PMOS transistor P1.
The control signal generating unit 1 receives a deep power down mode signal DPD and a power down mode signal PWD, and generates a control signal CON, and the PMOS transistor P1 controls the supply of a power voltage VDD in response to the control signal CON. Here, the deep power down mode signal DPD and the power down mode signal PWD are high active signals. Therefore, since the control signal CON is enabled to a high level when a DRAM enters into a deep power down mode or a power down mode, the PMOS transistor P1 is turned off and the power voltage VDD is interrupted.
As described above, the conventional semiconductor memory device interrupts the power voltage supplied to an internal circuit 2 to reduce the current consumption when the DRAM enters into the deep power down mode or the power down mode.
However, in states other than the deep power down mode or the power down mode, unnecessary current consumption can occur since the power voltage VDD is still supplied. In particular, in a case of a mobile DRAM requiring much less current consumption compared to a main memory or a graphic memory, there is a need to reduce the current consumption even in an idle state, in which all banks of the DRAM are precharged, other than the deep power down mode and the power down mode.